This application claims the priority right under Paris Convention of Japanese Patent Application Nos. 258545/1999 filed on Sep. 13, 1999 and 258261/2000 filed on Aug. 28, 2000, the entire disclosure of which is incorporated herein by reference.
(i) Field of the Invention
The present invention relates to a multilayer wring board suitable as a multilayer wiring board for a wafer block contact board constituting a part of a wafer block contact board used for executing a test (inspection) of a plurality of semiconductor devices formed on a wafer in the state of a wafer in a lump, and a manufacturing method thereof and others.
(ii) Description of the Related Art
The inspection for a plurality of semiconductor devices formed on a wafer is roughly divided into a product inspection by using a probe guard (electrical characteristic test) and a burn-in test which is a reliability test carried out after the former test.
The burn-in test is one of screening tests conducted in order to eliminate a semiconductor device which has an inherent defect or a device which develops trouble depending on a time and stress due to irregularities in manufacture. It can be said that the inspection using a probe card is an electrical characteristic test of a manufactured device, whereas the burn-in test is a thermal acceleration test.
If the burn-in test adopts an usual method by which a wafer is cut into chips by dicing after the electrical characteristic test conducted for each chip by using the probe card and the burn-in test is executed with respect to each packaged chip (1-chip burn-in system), the feasibility is poor in terms of cost. Therefore, development and practical application of a wafer block contact board (burn-in board) for conducting the burn-in test of multiple semiconductor devices formed on the wafer in a lump are advanced (Japanese patent application laid-open No. 231019-1995). A wafer block burn-in system using a wafer block contact board has the high feasibility in terms of cost and is an important technique in order to realize the trend of up-to-date technology such as the pair chip shipment or pair chip onboard.
The wafer block contact board has a different demand characteristic from that of the conventional probe card in that the wafer is inspected in a lump and the board is used for a heating test, and has the high demand level. If the wafer block contact board comes into practical use, the product inspection (electrical characteristic test) which has been carried out by using the probe card in the prior art can be conducted with respect to the wafer in a lump.
FIG. 12 shows one specific example of the wafer block contact board.
As shown in FIG. 12, the wafer block contact board has such a structure as that a membrane ring 30 having bumps is fixed on a multilayer wiring board for a wafer block contact board (which will be referred to as a multilayer wiring board hereinafter) 10 through an anisotropic conductive rubber sheet 20.
The membrane ring 30 having bumps bears a contact portion which directly comes into contact with a device to be inspected. In the membrane ring 30 having bumps, a bump 33 is formed on one side of a membrane 32 stretched across a ring 31 and a pad 34 is formed on the other side of the same. The bump 33 is associated with a rim of each semiconductor device (chip) on a wafer 40 or a pad formed on a center line (one chip corresponds to approximately 600 to 1000 pins and pads whose number is a product obtained by multiplying the number of pins by the number of chips are formed on the wafer) and the bumps 33 are formed at positions whose number is equal to the number of pads.
The membrane ring with bumps 30 bears a contact portion which directly comes into contact with a device to be inspected. In the membrane ring with bumps 30, a bump 33 is formed on one side of a membrane 32 stretched across a ring 31 and a pad 34 is formed on the other side of the same. The bump 33 is associated with a rim of each semiconductor device (chip) on a wafer 40 or a pad formed on a center line (one chip corresponds to approximately 600 to 1000 pins and pads whose number is a product obtained by multiplying the number of pins by the number of chips are formed on the wafer) and the bumps 33 are formed at positions whose number is equal to the number of pads.
The multilayer wiring board 10 has on an insulating board a wring for supplying a predetermined burn-in test signal and others to each bump 33 isolated on the membrane 32 through the pad 34. Since the wiring of the multilayer wiring board 10 is complicated, the multilayer wiring board 10 usually has a multilayer wiring structure such that a plurality of wiring layers are superimposed through an insulating film. Further, in the multilayer wiring board 10, the insulating board having the low coefficient of thermal expansion is used in order to avoid a connection failure caused by displacement of the pad 34 on the membrane 32 due to thermal expansion.
The anisotropic conductive rubber sheet 20 is an elastic body (which consists of silicon resin and has metal particles embedded in a pad electrode portion thereof) having the conductivity only in a direction vertical to a principal surface and electrically connects a terminal (not shown) of the multilayer wiring board 10 with a pad 34 on the membrane 32. When a convex portion of the anisotropic conductive rubber sheet 20 formed on the surface thereof is brought into contact with the pad 34 on the membrane 32, irregularities of the surface of the semiconductor wafer 40 and unevenness of the heights of the bumps can be absorbed, and the pad on the semiconductor wafer can be assuredly connected to the bump 33 on the membrane 32.
To each semiconductor device (chip) are formed a power supply of an integrated circuit, a ground and a pad electrode which functions as an input/output terminal (I/O terminal) for a signal (a power supply pad, a ground pad and an I/O pad) respectively, and a bump electrode of the wafer block contact board is formed and connected in one-to-one relationship with respect to all the pad electrodes of the semiconductor chip.
In the multilayer wiring board constituting a part of the above-described wafer block contact board, when the insulating film and the wiring layer are superimposed and formed on the insulating board having the coefficient of thermal expansion of not more than 10 ppm/xc2x0 C. (for example, a low expansion glass board), a crack may be generated in the insulating film. This tendency becomes prominent in the insulating film of the upper layer. For example, when the wiring layer, the insulating film, the wiring layer, the insulating film and the wiring layer are alternately superimposed on the insulating board in the mentioned order, a crack is apt to be generated in the insulating film of the upper layer (the insulating film of the second layer) in particular. On the other hand, when the insulating film and the wiring layer are alternately formed on the insulating board having the coefficient of thermal expansion of not less than 10 ppm/xc2x0 C. (for example, a board made of resin), a crack is not produced in the insulating film but displacement of the bump occurs when the coefficient of thermal coefficient of the wafer becomes large, which may result in the contact failure.
The cause for a crack generated in the insulating film can be considered as follows. That is, although the insulating film is generally formed by applying a liquid polymer antecedent which is then cured and highly polymerized, reduction in its cubic volume due to evaporation of a solvent or polymerization reaction generates the internal stress in the insulating film. The force produced across the insulating film (which will be referred to as a membrane stress) becomes large as a thickness of the insulating film is increased. Similarly, since the wiring of the wiring layer is partial in terms of the planar dimension, the insulating films adjacent to each other become integral at a position where no wiring is provided when the insulating film is superimposed. Thus, the thickness of the insulating film increases and the membrane stress also becomes high. Further, in general, since the coefficient of thermal expansion of the insulating film is larger than the coefficient of thermal expansion of the low expansion glass board or the wiring (10 ppm/xc2x0 C.), the thermal stress due to a difference in coefficient of thermal expansion is generated in the insulating film under the influence of heat during use of the multilayer wiring board or in the inspection process such as the burn-in test. It can be considered that these stresses are concentrated on a corner portion of a wiring pattern 5a in the multilayer wiring board formed by sequentially superimposing a wiring pattern 2a of the first layer, the insulating film 3 and the wiring pattern 5a of the second layer on the glass board 1 shown in FIGS. 5 and 6 or a corner portion of a rectangular contact hole (a square via) 12 for energizing the upper and lower wiring layers shown in FIG. 7(a) so that a crack 11 is generated in the insulating film 3 which is in contact with these corner portions.
In view of the above-described drawbacks, a first object of the present invention is to provide a multilayer wiring board capable of preventing a crack from being generated in an insulating film and avoiding the performance degradation of the multilayer wiring board or reduction in the reliability even though the insulating film and the wiring layer are alternately formed on the insulating board having the coefficient of thermal expansion of not more than 10 ppm/xc2x0 C. in particular.
Further, a second object of the present invention is to provide a multilayer wiring board for a wafer block contact board capable of preventing a crack from being generated in an insulating film and avoiding the performance degradation of the multilayer wiring board or reduction in the reliability and provide a wafer block contact board having the multilayer wiring board for a wafer block contact board.
Furthermore, a third object of the present invention is to provide a method for manufacturing a multilayer wiring board capable of manufacturing the multilayer wiring board in a simple process without adding a complicated process.
To this end, the present invention has the following structure.
(Structure 1) In a multilayer wiring board comprising: an insulating board; and a wring layer superimposed on the insulating board through an insulating film, a sum (total film thickness) d (xcexcm) of the thickness of the insulating film and internal stress f (MPa) of the insulating film satisfy the following relational expression (1):
dxc3x97f less than 700(MPaxc2x7xcexcm)xe2x80x83xe2x80x83(1)
(Structure 2) The multilayer wiring board according to the structure 1 is characterized in that the sum (total film thickness) d of the thickness of the insulating film is not less than 0.1 xcexcm and less than 50 xcexcm and the internal stress f of the insulating film f is not less than 14 MPa and less than 7000 MPa.
(Structure 3) The multilayer wiring board according to the structure 1 or 2 is characterized in that the coefficient of thermal expansion of the insulating board is not more than 10 ppm/xc2x0 C.
(Structure 4) In a multilayer wiring board comprising: an insulating board; and a wiring board superimposed on the insulating board through an insulating film, a corner portion of the wiring in the wiring board has such a shape as that a crack is hardly generated in the insulating film.
(Structure 5) In a multilayer wiring board comprising: an insulating board; and a plurality of wiring layers superimposed in the insulating board through an insulating film, an edge and/or a corner portion of the wiring in the wiring layer is so formed as to be shifted from an edge and/or a corner portion of the wiring of another wiring layer superimposed through the insulating film by not less than 100 xcexcm in a flat surface direction.
(Structure 6) In a multilayer wiring board comprising: an insulating board; and a wiring layer superimposed on the insulating board through an insulating film, a protective film is formed only at a contact terminal portion in an uppermost wiring layer.
(Structure 7) In a multilayer wiring board comprising: an insulating board; and a wiring layer superimposed on the insulating board through an insulating film, a contact terminal portion in an uppermost wiring layer of the multilayer wiring board has a conformation capable of preventing the contact terminal portion from being peeled.
(Structure 8) In a multilayer wiring board comprising: an insulating board; and a wiring layer superimposed on the insulating board through an insulating film, the thickness of a protective film at a contact terminal portion in an uppermost wiring layer of the multilayer wiring board is in a range of 300 angstrom to 30 xcexcm.
(Structure 9) In a multilayer wiring board comprising: an insulating board; and a wiring layer superimposed on the insulating board through an insulating film, an uppermost layer of a protective film at a contact terminal portion in an uppermost wiring layer of the multilayer wiring board is a thin film consisting of or mainly consisting of a noble metal having the thickness of not more than 0.8 xcexcm.
(Structure 10) In a multilayer wiring board comprising: an insulating board; and a wiring board superimposed on the insulating board through an insulating film, a protective film at a contact terminal portion in an uppermost wiring layer of the multilayer wiring board is an Ni/Au thin film sequentially formed on the uppermost wiring layer.
(Structure 11) The multilayer wiring board according to any of the structures 4 to 10 is characterized in that the coefficient of thermal expansion of the insulating board is not more than 10 ppm/xc2x0 C.
(Structure 12) The multilayer wiring board for a wafer block contact board according to any of the structures 1 to 11 is characterized in that the multilayer wiring board is a multilayer wiring board constituting a part of a wafer block contact board used for conducting a test of a plurality of semiconductor devices formed on a wafer in a lump.
(Structure 13) A wafer block contact board comprises: the multilayer wiring board having a wafer block contact board according to structure 12; a membrane ring with bumps bearing a contact portion which directly comes into contact with a device to be inspected; and anisotropic conductive rubber which electrically connects the multilayer wiring board to the membrane ring with bumps.
(Structure 14) In a multilayer wiring board manufacturing method comprising a step for superimposing an insulating film and a wiring layer on an insulating board, a condition under which a crack is generated in the insulating film is obtained from a sum (total film thickness) d (xcexcm) of the thickness of the insulating film and the internal stress f (MPa) of the insulating film, and the insulating film is formed in a range of combustions of d and f with which no crack is generated.
According to the structure 1, by satisfying the relational expression (1) described in the structure 1 with the sum (total film thickness) d of the thickness of the insulating film and the internal stress f of the insulating film, no crack is generated at a portion of the insulating film which comes into contact with a corner portion of the wiring pattern or the corner portion of a rectangular contact hole (a square via) for energizing the upper and lower wiring layers. On the other hand, a crack is generated in the insulating film which does not satisfy the relational expression (1).
It is to be noted that the sum (total film thickness) of the thickness of the insulating film means, for example, that a sum of the thickness of two insulating films if two layers of the insulating film exist and that the thickness of the insulating film if one layer of the insulating film exists.
Further, the internal stress of the insulating film varies depending on a material of the insulating film. In addition, even if the same polyimide is used, the internal stress of the insulating film changes depending on a manufacturer, a product number and others. It is to be noted that 1 MPa=1xc3x97107 dyn/cm2. The internal stress of the insulating film can be obtained by measuring and calculating a change in warpage of the board before and after formation of the insulating film.
According to the structure 2, if the insulating film satisfies the above-described relational expression (1) and the sum (total film thickness) d of the thickness of the insulating film and the internal stress f of the insulating film fall within a predetermined range described in the structure 2, the advantage of the structure 1 can be more prominently demonstrated.
If the sum (total film thickness) d of the thickness of the insulating film is less than 0.1 xcexcm, the durability or the insulation of the insulating film is deteriorated or a pin hole may be produced. Further, if it is not less than 50 xcexcm, it may be hard to prevent a crack, film peeling and others due to the film stress from occurring in some cases, and a via connection defect may be apt to be generated.
On the other hand, if the internal stress f of the insulating film is less than 14 MPa, the durability or the insulation of the insulating film is deteriorated or a pin bole may be produced. Further, if it is not less than 7000 MPa, it may be hard to prevent a crack, film peeling and others due to the film stress from occurring in some cases.
In light of the above description, it is preferable that the sum (total film thickness) d of the thickness of the insulating film is not less than 1 xcexcm and less than 50 xcexcm and that the internal stress f of the insulating film is not less than 14 MPa and less than 700 MPa.
The thickness and the internal stress of each insulating film can be arbitrarily set in the above-described predetermined range. However, taking the high frequency insulation and the thickness of irregularities (coverage of irregularities) formed by the wiring pattern into consideration, it is preferable that the thickness of each insulating film is not less than 5 xcexcm and the insulating film is formed as thick as possible within a range by which no crack is generated.
According to the structure 3, even if the coefficient of thermal expansion of the insulating board is not more than 10 ppm/xc2x0 C., a crack can not be generated in the insulating film. Further, when the coefficient of thermal expansion of the insulating board is not more than 10 ppm/xc2x0 C., it is possible to avoid the contact defect due to thermal expansion of the insulating board. In view of avoidance of the contact defect due to thermal expansion, it is preferable that the coefficient of thermal expansion of the insulating board is not more than 5 ppm/xc2x0 C. and close to the coefficient of thermal expansion of silicon.
Incidentally, if the coefficient of thermal expansion of the insulating board exceeds 10 ppm/xc2x0 C., the stress due to a difference in the coefficient of thermal expansion from the insulating film can not be a problem and a possibility of generation of a crack in the insulating film is low. In such a case, however, the advantage which can reduce the risk of generation of a crack can be obtained. More specifically, when taking only the stress between the insulating film and the insulating board into consideration, since the coefficient of thermal expansion of the insulating board which exceeds 10 ppm/xc2x0 C. approximates the coefficient of thermal expansion of the insulating film, the displacement of these members is small at the time of thermal expansion/contraction, and whereby an excessive force does not take effect.
According to the structure 4, by making the corner portion of the wiring in the wiring layer into such a shape as that a crack is hardly generated in the insulating film, occurrence of a crack in the insulating film can be suppressed.
Specifically, when the corner portion of the wiring pattern 5a shown in FIG. 6 or the corner portion of the rectangular contact hole (a square via) 12 for energizing the upper and lower wiring layers shown in FIG. 7(a) have an angle of approximately 90xc2x0 or a shaper angle, a crack 11 is apt to be generated in the insulating film 3. On the other hand, as shown in FIG. 6, when an angle xcex8 of the wiring at a bent portion is not less than 120xc2x0 or more preferably the bent portion of the wiring is rounded (eliminating an angle), generation of a crack in the insulating film can be suppressed. Additionally, adopting a contact hole without an angle (for example, a round via 13 such as shown in FIG. 7(b)) or a square via having a corner portion angle of not less than 120xc2x0 can suppress generation of a crack in the insulating film.
Incidentally, no crack is usually generated in the insulating film even at the corner portion of 90xc2x0 if the relational expression described in the structure 1 is satisfied, but the structure 4 can further reduce the risk and the like of partial occurrence of a crack due to irregularities in the film thickness.
When forming a plurality of wiring layers, it is preferable that the corner portion of the wiring in at least the uppermost wiring layer is made into such a shape as that a crack is hardly generated in the insulating film, but the corner portion of he wiring in any layer other than the uppermost layer can be also made in to such a shape which rarely generates a crack in the insulating film.
According to the structure 5, as shown in the right side of FIG. 9 for example, when the edge and/or the corner portion of the wiring in the wiring layer 2a is so formed as to be displaced from the edge and/or the corner portion of the wiring in any other wiring layer 5a superimposed through the insulating film 3 by not less than 100 xcexcm in the flat surface direction, it is possible to avoid concentration of stress due to superimposition of the edge portion or the corner portion of the wiring in the wiring layer in the thickness direction, thereby preventing a crack from being generated in the interlayer insulating film. In the similar view point, it is preferable that the edge and/or the corner portion is shifted by not less than 300 xcexcm in the flat surface direction.
Meanwhile, as shown in FIG. 8 and the left side of FIG. 9, when the edges and the like of the upper and lower wirings are superimposed two-dimensionally, the stress is concentrated at a portion sandwiched between the edges and the like, thereby producing a crack 11 in the interlayer insulating film 3.
Incidentally, although no crack is usually generated in the insulating film even though the edges and the like of the upper and lower wirings are superimposed two-dimensionally if the relational expression (1) described in the structure 1 is satisfied, the risk and the like of partial occurrence of a crack due to irregularities of the film thickness can be further reduced.
According to the structure 6, by forming a protective film only at the contact terminal portion in the uppermost wiring layer in the multilayer wiring board, the wiring layer can not be peeled off or a crack can not be generated in the insulating film due to excessive increase in the membrane stress as compared with the case where the protective film is provided across the wiring pattern. It is to be noted that electrical connection with an external circuit and the like can be assuredly attained if oxidation of the contact terminal portion which comes into contact with an external electrode can be prevented by the protective film.
As in the prior art, if the protective film is uniformly provided on the entire wiring pattern consisting of Cu and the like, the membrane stress excessively increases owing to the protective film so that the wiring layer may be peeled off or a crack may be generated in the insulating film. In case of the wiring pattern having no protective film provided thereon, although the wiring layer can not be peeled off or a crack can not be generated in the insulating film, oxidation of the wiring layer may occur or improvement of the electrical connectivity may be difficult.
As the contact terminal portion, there are a peripheral terminal (a ground terminal, a power supply terminal and others), a signal terminal and the like.
According to the structure 7, when the contact terminal portion in the uppermost wiring layer of the multilayer wiring board has a conformation capable of preventing the contact terminal portion from being peeled, peeling of the contact terminal portion can be effectively avoided.
Specifically, when a width Wxe2x80x2 (see FIG. 11) of the contact terminal portion is not more than 10 mm, peeling of the contact terminal portion can be effectively prevented. The contact terminal portion is peeled by the stress that an electroless plating film itself which consists of Ni/Au and the like formed at the contact terminal portion has. However, reducing the area of the contact terminal portion can decrease the stress the electroless plating film of Ni/Au and the like itself has in order to effectively avoid peeling of the contact terminal portion.
Further, as shown in FIG. 11, segmenting the contact terminal portion 14 by a hole 15 to be meshed can effectively prevent the contact terminal portion 14 from being peeled.
Moreover, as shown in FIG. 11, when the corner portion of the contact terminal portion 14 is rounded, the contact terminal portion can be effectively prevented from being peeled.
Further, thinning the protective film at the contact terminal portion can effectively prevent the contact terminal portion from being peeled, and this will be described in detail later.
As shown in the structure 8, it is preferable that the thickness of the protective film at the contact terminal portion is set in a range of 300 angstrom to 30 xcexcm. If the thickness of the protective film is less than 300 angstrom, the protection function may not be fully demonstrated. If the thickness of the same exceeds 30 xcexcm, the membrane stress may increase to cause a crack. In addition, when the film thickness exceeding 30 xcexcm is adopted, the protection function can not be further improved.
As shown in the structure 9, it is preferable that the uppermost layer of the protective film at the contact terminal portion is a thin film consisting of a noble metal or mainly consisting of a noble metal having a thickness of not more than 0.5 xcexcm.
Here, as the noble metal, there are Au, Ag, Pt, Ir, Os, Pd, Rh, Ru and others. Above all, a thin. film consisting of fine gold is preferable. That is because fine gold has the excellent ductility and flexibility and can follow expansion and contraction of the insulating film and the wiring so that a crack can not be generated in the insulating film. When the thickness of the noble metal thin film exceeds 0.5 xcexcm, a crack may be produced in the insulating film.
As a method for forming the protective film at the contact terminal portion, there are the electroless plating, the electrolytic plating, the sputtering method, the printing method and others, and any method can be appropriately selected in accordance with a film material, a formation position and others.
In order to form the protective film only at the contact terminal portion, a protective film such as resist is used to protect any portion other than the contact terminal portion and plating is then carried out, for example. As another method for forming a protective film only at the contact terminal portion, there is a method by which the protective film is formed on the entire surface of the uppermost wiring layer (before patterning) by the electrolytic plating, the wiring layer and the protective film are continuously etched and the protective film on the wiring layer is partially removed by etching. Incidentally, although the electrolytic plating can further reduce interfusion of impurities as compared with the electroless plating, formation of the protective film with respect to the isolated wiring pattern is difficult. The Au film can be etched by using a water solution of iodine and potassium iodide.
As shown in the structure 10, it is preferable that the protective film of the contact terminal portion is an Ni/Au thin film sequentially formed on the uppermost wiring layer.
According to such a conformation, it is possible to obtain the protective film which has the excellent adhesiveness relative to the uppermost wiring layer composed of, e.g., a Cu wiring and also has the good oxidation resistance and stability.
In case of the Ni/Au plating using the electroless plating, the thickness of the protective film is preferably approximately 0.4 to 2.0 xcexcm for Ni and approximately 0.05 to 0.8 xcexcm for Au, and more preferably approximately 1 xcexcm for Ni and approximately 0.1 to 0.5 xcexcm for Au. That is because plating advances while Ni is substituted by Au and the Ni film thickness which is approximately two-fold or three-fold of the Au film thickness is hence required in case of the electroless plating. Further, the uppermost wiring layer does not peel under such a condition. On the other hand, in case of the electroless plating, when the thickness exceeds approximately 2 xcexcm for Ni and 0.8 xcexcm for Au, peeling of the wiring layer occurs.
It is to be noted that, the multilayer wiring board described in the above-described structures 1 to 9 also includes the conformation that the Ni thin film is formed on the entire surface of the uppermost Cu wiring layer and the Au protective film is formed only at the contact terminal portion.
According to the structure 1, a crack may not be generated in the insulating film. Further, when the coefficient of thermal expansion of the insulating board is not more than 10 ppm/xc2x0 C., the contact defect due to thermal expansion of the insulating board can be avoided. In view of avoidance of the contact defect due to thermal expansion, it is preferable that the coefficient of thermal expansion of the insulating board is not more than 5 ppm/xc2x0 C. and approximates the coefficient of thermal expansion of silicon.
According to the structure 12, it is possible to obtain the multilayer wiring board for a wafer block contact board having no crack in the insulating film.
According to the structure 13, there can be obtained a wafer block contact board having the multilayer wiring board for a wafer block contact board with no crack in the insulating film and having the excellent reliability and durability.
According to the structure 14, it is possible to manufacture the multilayer wiring board having no crack generated in the insulating film by a simple process without adding a complicated process.